In very and ultra large scale integration (VLSI and ULSI) circuits, insulating or dielectric material, such as silicon dioxide, of the semiconductor device is patterned with several thousand openings for the conductive lines and vias which are filled with conductive material, such as metal, and serve to interconnect the active and/or passive elements of the integrated circuit. The interconnection process is used for forming the multi-level signal lines of metal, such as a copper, in an insulating layer, such as polyimide, of a multi-layer substrate in which the semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings are also formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. During anisotropic etching of the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and the grooves are filled with metal. The excess metal was removed by CMP (chemical mechanical polishing) techniques. One of the advantages of dual damascene processing is that it permits the filling of both the conductive grooves and the vias with metal at the same time, thereby eliminating process steps. Furthermore, with single damascene, since two different metal deposition steps were used, an interface exists between the conductive via and the conductive wiring.
One dual damascene method described in U.S. Pat. No. 5,705,430 uses a sacrificial via fill. In this method, a first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is disposed on the first layer. Using a conductive line pattern, aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. The sacrificial material is not etchable by the etchant performing the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which a first insulating layer is resistive or less selective. Conductive material is then deposited in the conductive line and the via openings.
U.S. Pat. No. 5,635,423 describes a simplified dual damascene process for multi-level metallization and interconnection structure. An opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and the first insulative layer. The trench and the via are then simultaneously filled with conductive material. Alternatively, the via is defined on the etch-stop layer. The resist layer is then deposited and masked for the trenches. The large opening for the trench and the smaller opening for the via are simultaneously etched. The trench and the via are then simultaneously filled with conductive material.
Although both of the above described processes provide the desired dual damascene structure, there is a continuing goal of simplifying the process even further and thereby making it less expensive.